1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to the shape of a storage node electrode in a charge storage type capacitor in a DRAM having memory cells comprising one transistor and one stacked capacitor for charge storage.
2. Description of the Prior Art
DRAM stores data in a capacitor for charge storage in the form of electric charges. In view of the stable operation and the memory retaining time of the DRAM, the capacitance of the capacitor for charge storage should preferably be as large as possible. But, on the other hand, the size of memory cells should be made as small as possible for higher integration of the DRAM. This reduces the projective plane area available for the capacitor. The projective plane area is smaller than the size of the memory cells. In order to solve the dilemma, the structure for the capacitor for charge storage in a DRAM having the memory cell of one transistor and one capacitor has undergone a change from the planer type to the trench type and further to the stacked type.
A typical example of such stacked type DRAM is disclosed in ISSCC DIGEST OF TECHNICAL PAPERS, pp. 250-251; February, 1985.
On the surface of a p-type silicon substrate is selectively provided field oxide films and active areas surrounded by the field oxide films. Gate insulation films are provided on the surface of the active areas. Plural word lines are provided substantially parallel to each other upon the field oxide films and the gate insulation films on the memory cell array of a DRAM. The word lines are formed with an N.sup.+ type polycrystal silicon film and the like. The N.sup.+ type diffused layer which is self-matched with the word lines is provided on the active area. The transistor of the memory cells comprises the N.sup.+ type diffused layer and the word lines. The field oxide films, the gate insulation films and the word lines are covered with the first insulation film between layers. The first insulation film may be formed with the silicon oxide film, for example, by CVD method. Node contact holes are formed between the word lines on the gate insulation film and the adjacent word lines on the field oxide film to extend to and reach the N.sup.+ type diffused layer. The storage node electrode is connected to the N.sup.+ diffused layer via the node contact holes, extends over the word lines on the gate insulation film via the first insulation film, and further over the word lines on the field oxide film adjacent to the word lines via the first insulation film simultaneously. The storage node electrode may be formed with an N.sup.+ type polycrystal silicon film. The storage node electrode is covered with the capacitance insulation film which in turn is covered with the cell plate electrode. The storage node electrode, the capacitance insulation film and the cell plate electrode form a capacitor for storing electric charge. The capacitor for storing electric charge and the first insulation film between layers are covered with the second insulation film between layers. Between the two word lines adjacent to each other within the same active area is provided a bit contact hole to extend to the N.sup.+ type diffused layer between these word lines. The substantially parallel plural bit lines on the second insulation film between layers are orthogonally intersecting word lines and connected to the N.sup.+ type diffused layer via the bit contact hole.
The aforementioned report does not mention about the structure of the peripheral circuitry of the memory cells, but it is generally formed as below. The field oxide films and active areas of the peripheral circuitry are formed simultaneously with the field oxide films and the active areas of the memory cells. The gate insulation film, the gate electrode and the N.sup.+ type diffused layer of the transistor which are the components of the peripheral circuitry are respectively formed simultaneously with the gate insulation film, the word lines and the N.sup.+ type diffused layer of the memory cells. The contact holes of the peripheral circuitry are formed simultaneously with the bit contact holes. The metal wiring of the peripheral circuitry is formed simultaneously with the bit lines.
Capacitance of the capacitor for storing electric charges is determined by the permittivity and the film thickness of the capacitance insulation film and the opposing areas of the two electrodes. The opposing areas are calculated by adding the surface areas of the top and the side faces of the storage node electrode.
When the size of the memory cells is further reduced in the capacitor for storing electric charges of the aforementioned structure, the capacitance decrease may be prevented by such methods as of further decreasing the film thickness of the capacitance insulation film, forming the capacitance insulation film with a material having a still higher permittivity, and increasing the opposing areas. These three methods are independent of each other. However, it is quite difficult to increase the opposing area without imposing an extra burden on the processibility of the storage node electrode.